Electronic calculator systems of the type wherein all of the main electronic functions are integrated in a single large cell integrated semiconductor chip or in a small number of such chips, are described in the following U.S. Patents, which are assigned the assignee of this invention:
The concepts of these prior applications have made possible vast reductions in the cost of small personal-size calculators. Continuing efforts to reduce the cost of these products include the design of a single chip calculator system for use in large capacity calculators, such as scientific or business calculators. The chip disclosed herein may be utilized in scientific or business calculators for instance, because this chip has provisions for a number of storage registers, in addition to operational registers, as well as sufficient capacity to solve the more complicated mathematical expressions and functions used in scientific and business calculators including, for example, trigonometric and logarithmic relationships.
The present invention relates to a non-sequential counter. An entire electronic calculator system including the non-sequential counter of this invention is disclosed. The electronic calculator disclosed is a serial, word organized calculator. It should be evident, however, that the invention disclosed is operable with other types of electronic calculators and devices. In the prior art, it is known to provide a non-sequential counter having N bit positions (and therefore 2N inverters) wherein the feedback term (i.e. the bit to be shifted into the least significant bit position) is generated by an exclusive OR circuit responsive to the two most significant bit positions. That is, if the two most significant bits are of the same state (either both ones or both zeros), a logical one is shifted into the least significant bit position for the next number to be generated. By using this prior art method, the counter will count through 2.sup.N -1 states, which is one less than the number of states possible for a counter having N bit positions. This result occurs because this prior art counter is incapable of counting to a binary number having a one in each one of the bit positions. In the prior art, it was known to use additional logic circuitry for forcing the counter into a state where logical ones occupied every bit position and to force the counter of that particular state. For example, see FIGS. 9 and 19 and the discussion relating thereto in U.S. Pat. No. 3,989,939. While this prior art counter was effective for counting through the 2.sup.N states by using the additional logical circuitry, the additional logical circuitry highly complicated the design of the counter.
It is therefore one object of this invention to provide a simplified non-sequential counter. It is another object of this invention to provide a non-sequential counter having N bit positions and capable of counting through 2.sup.N states. It is yet another object of this invention to provide an N bit position non-sequential counter capable of counting through 2.sup.N states without the necessity of circuitry to force the counter into and out of a particular state.
The foregoing objects are achieved according to the present invention as is now described. In a preferred embodiment of the invention, a non-sequential shift register is provided on an electronic calculator semiconductor chip. The non-sequential counter utilized on the calculator chip is a three bit counter and is provided as part of the segment scan circuitry for driving the segments of the characters of the display. The counter's output is also provided as an input to the display decoder for decoding which segments are to be actuated during a particular segment scanning cycle. The three bit non-sequential counter includes six inverters coupled by clocked transfer gates to form a shift register. An output from each of the inverter stages is provided to a feedback logic circuit which decodes the present state of the counter and determines whether a logical zero or one should be loaded into the least significant bit position of the counter during the next incrementing cycle. In the embodiment disclosed, the feedback logic circuit comprises an AND gate responsive to the output of the least significant bit position in false logic and the output of the second bit position in true logic, an OR gate responsive to the AND gate and to the output of the most significant bit position in true logic, another OR gate responsive to the output of the least significant bit position in true logic and the outputs of the second bit position and the most significant bit position in false logic and a NAND gate responsive to the outputs of the two OR gates. The NAND gate provides the bit to be inserted into the least significant bit position of the shift register. Further, counters having more than three bit positions are disclosed as well as how the particular arrangement of the feedback logic gates may be developed.